The performance and reliability of a MOS device is seriously affected by lowering of the threshold voltage, that is, the gate voltage allowing the drain current to flow, as well as degradation of the mobility of carriers drawn to the field. Threshold voltage lowering known as the short channel effect associated with microstructuring is due to the widening of the depletion region. Mobility degradation results from increasing electric field due to higher channel concentration. The latter affects the high-speed performance of the device while the former affects the correct operating point.
To overcome the problems described above, a MOS device with a structure called NUDC has been developed as discussed in Y. Okumura et al., `A Novel Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET for High Current Drivability and Threshold Voltage Controllability`. IEDM Tech. Dig. p. 391, 1990. In this device, the concentration of the channel near the source to drain is increased to suppress the widening of the depletion region while the concentration in the middle of the channel is decreased to improve the mobility.
FIG. 9A shows a schematic cross section of an n-type NUDC MOSFET (field effect transistor). As the figure shows, a gate electrode 104 is formed via a gate oxide 103 over a low concentration p.sup.- well 102 formed on a p-type silicon substrate 101 wherein the gate length (channel length) is patterned to be `L` in the figure. On each side of the gate electrode 104, each of high concentration n.sup.+ regions 105 and 106 is formed as the source and drain respectively in a self-aligned manner with the gate electrode 104. Beneath the n.sup.+ regions 105 and 106, high concentration p.sup.+ regions 107 and 108 are formed. One end of each of the p.sup.+ regions 107 and 108 reaches the base of the gate electrode 104, that is, part of the channel region (.DELTA.L in the figure from the source and the drain respectively).
FIG. 9B shows the profile of the channel region concentration formed beneath the gate electrode 104 in FIG. 9A. The horizontal axis indicates a position in the direction of the channel length. The vertical axis shows concentration. As shown in this figure, concentration N.sub.TH1 is high since the p.sup.+ regions 107 and 108 reach part of the channel region, that is, from 0 to .DELTA.L and from L-.DELTA.L to L in the figure, adjacent to the n.sup.+ regions 105 and 106 as the source and drain respectively. On the other hand, concentration N.sub.TH2 of the p.sup.- well 102 is low in the middle of the channel region (from .DELTA.L to L-.DELTA.L). Therefore, a semiconductor device with the structure thus described suppresses lowering of the threshold voltage due to the widening depletion region as well as suppresses degradation of the carrier mobility.
A semiconductor device with the NUDC structure has been manufactured using the oblique rotating ion implantation technique. This ion implantation technique as shown in FIG. 9A, is designed to implant impurity (p impurity in this example) of the same conductivity type as the p.sup.- well 102 into the region other than the area beneath the gate electrode 104 in a rotating manner in an oblique direction.
However, the oblique rotating ion implantation technique makes it difficult to control the concentration of the substrate (the p.sup.- well 102 in FIG. 9A) and the profile in the direction of the dose depth. Another problem is that when the gate length is shortened due to microstructuring of the device, oblique rotating implantation may allow the impurity to reach under the gate electrode, leading to loss of the low concentration region in the center of the channel region.
In general, the current drivability of a MOS transistor depends on the impurity concentration in the channel region. If the concentration becomes higher, the mobility will be reduced while the threshold voltage goes high. This leads to the degradation of the current drivability of the MOS transistor. Therefore, while the conventional NUDC MOS transistor can suppress the lowering of the threshold voltage due to the short channel effect, the degradation of the current drivability may occur at both sides of the channel region (adjacent to the source-drain region) when the concentration thereof is higher. The current drivability of the MOS transistor itself may be thus reduced.